As a Staff/Senior QPU Layout Engineer, you will drive the physical implementation and verification for a cutting-edge quantum processor platform. You’ll be a go-to expert for full-chip and block-level layouts, ensuring designs are reliable, manufacturable, and ready for tapeout.

You will be hands-on with layout while also contributing to the transition from research prototypes to production using industry-standard semiconductor tools and processes.You should enjoy solving problems with solutions flexible to changing rules while maintaining engineering discipline.

The role involves collaborating closely with experimentalists, device modellers, and designers, bridging research and industry-standard approaches.

It is not a conventional IC layout role: our process is bespoke and evolving, requiring flexibility and strong problem-solving. However, it’s grounded in industrial tools and practices and thus best suited to those with a strong industry foundation.

• Implement block-level and chip-level physical layouts for spin qubits in SiMOS quantum dots from concept through integration and tapeout using standard EDA tools.

• Drive layout work to completion using industry best practices to ensure manufacturability and scalability.

• Deliver layouts that meet agreed physical verification and sign-off criteria, and own tapeout readiness.

• Interpret EM analysis, adjusting layouts to meet reliability and integration goals.

• Create or adapt minimal schematics or netlists to support LVS and verification flows.

• Contribute to the definition and maintenance of PDKs, layout methodologies, conventions, and abstractions.

• Lead design reviews, tapeout planning, and technical documentation.

• Coach or manage layout engineers as the team grows.

• Collaborate closely with interdisciplinary teams, translating research intent into manufacturable layouts.

• Masters in Engineering, Physics, or related field, or equivalent professional experience.

• 6+ years leading chip layouts through tapeout in research-driven or novel technology environments.

• Strong proficiency with Cadence Virtuoso for full-chip and block-level layout and verification flows.

• Strong understanding of layout verification (DRC/LVS/ERC) using Calibre or equivalent.

• Experience interpreting EM simulation results to optimise layout for signal integrity and reliability.

• Proven ability to execute layouts evolving process nodes where formal design rules are incomplete and engineering judgment drives signoff decisions.

• Track record of effective cross-functional collaboration across disciplines and domains.

• Experience with quantum devices, CMOS process integration, and/or 3D integration.

• Experience developing PDKs, rule decks, or working closely with EDA teams.

• Scripting or automation experience (SKILL, Python, or similar).

• Experience managing a small team of layout engineers.

• Be part of a creative, world-leading team

• Competitive salary and share options scheme

• Contributory pension scheme

• Group private medical insurance scheme

• Life Assurance

Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010.